SI4713-B30-GMR【PDF 27/42 页】IC TX FM RADIO RPS/RDS 20UQFN

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Si4712/13-B30

Rev. 1.1

5.8. Pre-emphasis and De-emphasis

Pre-emphasis and de-emphasis is a technique used by

FM broadcasters to improve the signal-to-noise ratio of

FM receivers by reducing the effects of high-frequency

interference and noise. When the FM signal is

transmitted, a pre-emphasis filter is applied to

accentuate the high audio frequencies. All FM receivers

incorporate a de-emphasis filter that attenuates high

frequencies to restore a flat frequency response. Two

time constants are used in various regions. The pre-

emphasis time constant is programmable to 50 or 75 祍

and is set by using the TX_PREEMPHASIS property.

5.9. RDS/RBDS Processor (Si4713 Only)

The Si4713 implements an RDS/RBDS* processor for

symbol encoding, block synchronization, and error

correction. Digital data can be transmitted with the

Si4713 RDS/RBDS encoding feature.

RDS transmission is supported with three different

modes. The first mode is the simplest mode and

requires no additional user support except for pre-

loading the desired RDS PI and PTY codes and up to

12 8-byte PS character strings. The Si4713 will transmit

the PI code and rotate through the transmission of the

PS character strings with no further control required

from outside the device. The second mode allows for

more complicated transmissions. The PI and PTY

codes are written to the device as in mode 1. The

remaining blocks (B, C, and D) are written to a 252 byte

buffer. This buffer can hold 42 sets of BCD blocks. The

Si4713 creates RDS groups by creating block A from

the PI code, concatenating blocks BCD from the buffer,

and rotating through the buffer. The BCD buffer is

circular; so, the pattern is repeated until the buffer is

changed. Finally, the third mode allows the outside

controller to burst data into the BCD buffer, which

emulates a FIFO. The data does not repeat, but, when

the buffer is nearly empty, the Si4713 signals the

outside device to initiate another data burst. This mode

permits the outside device to use any RDS functionality

(including open data applications) that it wants.

*Note: RDS/RBDS is referred to only as RDS throughout the

remainder of this document.

5.10. Tuning

The frequency synthesizer uses Silicon Laboratories

proven technology including a completely integrated

VCO. The frequency synthesizer generates the

quadrature local oscillator signal used to upconvert the

low intermediate frequency to RF. The VCO frequency

is locked to the reference clock and adjusted with an

automatic frequency control (AFC) servo loop during

transmission.

The tuning frequency can be directly programmed with

commands. For example, to tune to 98.1 MHz, the user

writes the TX_TUNE_FREQ command with an

argument = 9810.

The Si4712/13 supports channel spacing of 50, 100, or

200 kHz.

5.11. Reference Clock

The Si4712/13 reference clock is programmable,

supporting RCLK frequencies from 31.130 kHz to

40 MHz. The RCLK frequency divided by an integer

number (the prescaler value) must fall in the range of

31,130 to 34,406 Hz. Therefore, the range of RCLK

frequencies is not continuous below frequencies of

311.3 kHz. The default RCLK frequency is 32.768 kHz.

Please refer to AN332: Universal Programming Guide

for using other RCLK frequencies.

5.12. Control Interface

A serial port slave interface is provided; this allows an

external controller to send commands to the Si4712/13

and receive responses from the device. The serial port

can operate in three bus modes: 2-wire mode, SPI

mode, or 3-wire mode. The Si4712/13 selects the bus

mode by sampling the state of the GPO1 and

GPO2/INT

pins on the rising edge of RST

. The GPO1

pin includes an internal pull-up resistor that is

connected while RST

is low, and the GPO2/INT

includes an internal pull-down resistor that is connected

while RST

is low. Therefore, it is only necessary for the

user to actively drive pins that differ from these states.

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